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74F382 4-Bit Arithmetic Logic Unit
May 1988 Revised October 2000
74F382 4-Bit Arithmetic Logic Unit
General Description
The 74F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select input codes force the Function outputs LOW or HIGH. An Overflow output is provided for convenience in twos complement arithmetic. A Carry output is provided for ripple expansion. For high-speed expansion using a Carry Lookahead Generator, refer to the 74F381 data sheet.
Features
s Performs six arithmetic and logic functions s Selectable LOW (clear) and HIGH (preset) functions s LOW input loading minimizes drive requirements s Carry output for ripple expansion s Overflow output for twos complement arithmetic
Ordering Code:
Order Number 74F382SC 74F382SJ 74F382PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
(c) 2000 Fairchild Semiconductor Corporation
DS009529
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74F382
Unit Loading/Fan Out
Pin Names A0-A3 B0-B3 S0-S2 Cn Cn + 4 OVR F0-F3 Description A Operand Inputs B Operand Inputs Function Select Inputs Carry Input Carry Output Overflow Output Function Outputs U.L. HIGH/LOW 1.0/4.0 1.0/4.0 1.0/1.0 1.0/5.0 50/33.3 50/33.3 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-2.4 mA 20 A/-2.4 mA 20 A/-0.6 mA 20 A/-3.0 mA
-1 mA/20 mA -1 mA/20 mA -1 mA/20 mA
Functional Description
Signals applied to the Select inputs S0-S2 determine the mode of operation, as indicated in the Function Select Table. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs the arithmetic functions for either active HIGH or active LOW operands, with output levels in the same convention. In the Subtract operating modes, it is necessary to force a carry (HIGH for active HIGH operands, LOW for active LOW operands) into the Cn input of the least significant package. Ripple expansion is illustrated in Figure 2. The overflow output OVR is the Exclusive-OR of Cn + 3 and Cn + 4; a HIGH signal on OVR indicates overflow in twos complement operation. Typical delays for Figure 2 are given in Figure 1.
Function Select Table
Select S0 L H L H L H L H
H = HIGH Voltage Level L = LOW Voltage Level
S1 L L H H L L H H
S2 L L L L H H H H
Operation Clear B Minus A A Minus B A Plus B AB A+B AB Preset
Path Segment A1 or B1 to Cn + 4 Cn to Cn + 4 Cn to Cn + 4 Cn to F Cn to Cn + 4, OVR Total Delay
Toward F 6.5 ns 6.3 ns 6.3 ns 8.1 ns -- 27.2 ns
Output Cn + 4, OVR 6.5 ns 6.3 ns 6.3 ns -- 8.0 ns 27.1 ns
FIGURE 1. 16-Bit Delay Tabulation
FIGURE 2. 16-Bit Ripply Carry ALU Expansion
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74F382
Truth Table
Inputs Function CLEAR B MINUS A S0 L H S1 L L S2 L L Cn L H L L L L H H H H A MINUS B L H L L L L L H H H H A PLUS B H H L L L L L H H H H AB L L H X X L X H A+B H L H X X X L H AB L H H X X X L H PRESET H H H X X X L H
H = HIGH Voltage Level L = LOW Voltage Level
Outputs An X X L L H H L L H H L L H H L L H H L L H H L L H H L L H H H L L H H H L L H H H L L H H H Bn X X L H L H L H L H L H L H L H L H L H L H L H L H L H L H L L H L H H L H L H H L H L H H F0 L L H L L H L H H L H L L H L H H L L H H L H L L H L H H L H L H H H H L L L H H H H H H H F1 L L H H L H L H L L H L H H L L H L L H H H L L L H L H H L H L H H H H L L L H H H H H H H F2 L L H H L H L H L L H L H H L L H L L H H H L L L H L H H L H L H H H H L L L H H H H H H H F3 L L H H L H L H L L H L H H L L H L L H H H L L L H L H H L H L H H H H L L L H H H H H H H OVR H H L L L L L L L L L L L L L L L L L L L L L L L L L L L H H L L L L H H L H L H L L L L H Cn + 4 H H L H L L H H L H L L H L H L H H L L L H L H H H L L L H H L L L L H H L H L H L L L L H
X = Immaterial
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74F382
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F382
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA)
-65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C
+4.5V to +5.5V
-0.5V to VCC -0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics over Operating Temperature Range unless otherwise specified
Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current 4.75 3.75 -0.6 -2.4 -3.0 IOS ICC Output Short-Circuit Current Power Supply Current -60 54 -150 81 mA mA Max Max mA Max 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 7.0 50 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A A V A Min Min Min Max Max Max 0.0 0.0 VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (S0 - S2) VIN = 0.5V (A0 - A3, B0 - B3) VIN = 0.5V (Cn) VOUT = 0V
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74F382
AC Electrical Characteristics
TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Cn to Fi Propagation Delay Any A or B to Any F Propagation Delay Si to Fi Propagation Delay Ai or Bi to Cn + 4 Propagation Delay Si to OVR or Cn + 4 Propagation Delay Cn to Cn + 4 Propagation Delay Cn to OVR Propagation Delay Ai or Bi to OVR 3.0 2.5 4.0 3.0 6.5 4.0 3.5 3.5 7.0 5.0 2.5 3.5 3.5 2.5 7.0 3.0 VCC = +5.0V CL = 50 pF Typ 8.1 5.7 10.4 8.2 11.0 8.2 6.0 6.5 12.5 9.0 5.6 6.3 8.0 7.1 11.5 8.0 Max 12.0 8.0 15.0 11.0 20.5 15.0 8.5 9.0 16.5 12.0 8.0 9.0 11.0 10.0 15.5 10.5 TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 3.0 2.5 3.5 2.5 5.5 4.0 3.5 3.5 7.0 5.0 2.0 2.0 3.5 2.5 7.0 3.0 Max 13.0 9.0 17.0 12.0 21.5 17.5 11.0 10.5 17.5 14.5 9.0 10.0 13.0 11.0 16.5 11.5 ns ns ns ns ns ns ns ns Units
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74F382
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
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74F382
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74F382 4-Bit Arithmetic Logic Unit
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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